Modeling cache performance for embedded systems

This paper presents a cache performance model for embedded systems. The need efficient design in systems has led to the exploration of various methods optimal configurations processor. Better users’ experiences are realized by improving parameters work hit rate estimation that can be used explore using Bourneli’s binomial cumulative probability based on application reuse distance profiles. presented was evaluated three mibench benchmarks which bitcount, basicmath and FFT 4kb, 8kb, 16kb, 32kb 64kb sizes under 2-way, 4-ways, 8-ways 16-ways set associative configurations, all least recently-used (LRU) replacement policy. results were compared with obtained sim-cheetah from simplescalar simulators suite. mean errors basicmath, 0.0263%, 2.4476%, 1.9000% respectively. Therefore, error is equal 1.4579%. margin below 5% within acceptable limits showing estimate rates options.